Semiconductor manufacturing utilizes processing steps such as patterning through lithography, various methods of layer deposition and removal, and thermal cycling, etc. All of these processes can degrade electrical properties of a device formed by the processing steps. Chemical-mechanical planarization (CMP) is a method of layer removal which relies on pattern uniformity within the layer. To enhance pattern uniformity and avoid associated performance degradation for an array of devices, dummy cell insertion is utilized within unused space residing between active devices within a region of the array by an automated cell insertion routine or other means. As device sizes shrink through node-to-node scaling, the relative contribution of to the performance degradation resulting from CMP and other pattern uniformity dependent processing steps increases. Matching of device parametrics between analog devices located in different regions of a circuit layout must be considered when modeling function of a circuit design to insure correct behavior of a manufactured semiconductor circuit.